The present invention relates to a liquid crystal display, and more particularly concerns an active-matrix driving-type liquid crystal display that is preferably used in the field of flat panel displays.
Conventionally, liquid crystal displays using a nematic liquid crystal have been widely used in watches, calculators and other articles as segment-type liquid crystal displays. In recent years, thanks to their features such as thinness, light-weight and low power consumption, the liquid crystal displays of this type have been used as various displays for word processors, personal computers and navigation systems, and have rapidly broaden their markets. In particular, much attention has been focused on liquid crystal displays of the active-matrix type in which active elements such as TFTs (Thin Film Transistors) are used as switching elements, with pixels arranged in a matrix format.
There have been ever-increasing demands for the liquid crystal displays of this type in wider fields including displays of note-type or desktop-type personal computers, portable televisions and space-saving televisions, and displays of digital cameras and digital video cameras, because they have advantages, such as a great reduction in thickness (depth), easiness for providing full-color devices and smaller power consumption, as compared with, for example, CRTs (Cathode Ray Tube).
A conventional active-matrix-type liquid crystal display of the light-transmission type is constituted by a light-transmitting active-matrix substrate on which an active-matrix circuit consisting of TFTs is formed, an opposing substrate having common electrodes formed thereon that is aligned face to face with the active-matrix substrate, and a liquid crystal layer that is interpolated between the active-matrix substrate and the opposing substrate.
FIG. 23 is a circuit diagram that schematically shows one example of the active-matrix circuit on the active-matrix substrate. A plurality of pixel electrodes 91 are formed on the active-matrix substrate in a matrix format. Normally, the pixel electrodes 91 are arranged in the row direction and column direction, with several hundreds pixels being aligned in each direction.
Moreover, common electrodes (not shown) are formed on the opposing substrate, not shown, in a manner so as to face the pixel electrodes 91 through the liquid crystal layer, and a voltage is applied to the liquid crystal layer by the pixel electrodes 91 and the common electrodes. Here, in general, the common electrodes are formed virtually on the entire surface of the opposing substrate.
Furthermore, TFTs 92, which are active elements serving as switching means for selectively driving the pixel electrodes 91, are formed on the active-matrix substrate, and connected to the pixel electrodes 91. In order to provide color display, color filter layers (not shown) of red, green, blue, etc. are formed on the opposing substrate, the active-matrix substrate or another member.
Scanning lines 93 are connected to the gate electrodes of the TFTs 92, and gradation signal lines 94 are also connected to the source electrodes of the TFTs 92. The scanning lines 93 and the gradation signal lines 94 are allowed to pass around the pixel electrodes 91 arranged in the matrix format, and placed so as to intersect each other. Gate signals are inputted through the scanning lines 93 so that the TFTs 92 are controlled and driven. Moreover, at the time of driving the TFTs 92, data signals are inputted to the pixel electrodes 91 through the gradation signal lines 94. Here, scanning signal input terminals 93a are connected to ends of the scanning lines 93, and data signal input terminals 94a are connected to ends of the gradation signal lines 94.
Moreover, the drain electrodes of the TFTs 92 are connected to the pixel electrodes 91, and also connected to added capacitances 95. Then, each electrode on the opposing side of the added capacitance 95 with respect to the insulating layer is connected to each of common electrodes 96. The added capacitance 95 is used for holding a voltage that is applied to the liquid crystal layer.
In the active-matrix-type liquid crystal display, the liquid crystal layer sandwiched between the active-matrix substrate and the opposing substrate is normally set to have an average thickness of 3.0 to 4.5 xcexcm; thus, a liquid crystal capacitance is formed by the pixel electrodes 91, the common electrodes and the liquid crystal layer. Here, the added capacitances 95 are connected in parallel with the liquid crystal capacitance.
In the active-matrix-type liquid crystal display having the above-mentioned arrangement, however, the scanning lines 93 and the gradation signal lines 94 are arranged to intersect each other on the same substrate, and these large number of intersections are highly susceptible to short-circuiting and the resulting defects. This has caused a reduction in the yield and high costs.
In order to solve the problem with such a construction having intersecting scanning lines and gradation signal lines on the same substrate, a liquid crystal display, for example, as shown in FIG. 24, has been proposed. This liquid crystal display has a construction explained as follows:
A number of switching elements 101 with three terminals, constituted by amorphous silicon semiconductors, are installed on one of substrates 100 in a matrix format. Here, a scanning line 102 is connected to one terminal of the switching element 101 for each line, and a reference signal line 103 is connected to another terminal of the switching element 101 for each line. Moreover, a pixel electrode 104 is connected to the other terminal of each of the switching elements 101.
A plurality of gradation signal lines 106 are placed in a direction orthogonal to the scanning lines 102 on an opposing substrate 105 that is placed in a manner so as to face the substrate 100. The gradation signal lines 106 also function as opposing electrodes at portions facing pixel electrodes 104.
In this arrangement, the scanning lines and the gradation signal lines are not made to intersect each other on the same substrate, and placed on respectively different substrates; therefore, it is possible to reduce the rate of occurrence of line defects. Thus, it becomes possible to improve the yield and also to reduce costs. Additionally, hereinafter, the construction of a liquid crystal display shown in FIG. 23 is referred to as the present construction, and the construction of a liquid crystal display shown in FIG. 24 is referred to as xe2x80x9copposing source constructionxe2x80x9d.
As described above, there have been ever-increasing demands for large-size panels and high-precision devices with respect to liquid crystal displays. One of the major problems with the achievement of the large-size panels and high-precision devices is degradation in the display quality due to signal delays. Here, the signal delays refer to signal delays in the common signal line in the case of the present construction, and also refer to signal delay in the reference signal line in the opposing source construction.
As the panel size increases, the signal wire becomes longer, thereby increasing the resistivity of the signal wire itself and the parasitic capacitance imposed on the signal wire. Since the size of the signal delay is in proportion to a product of the resistivity of the signal wire and the load capacitance, the enlargement of the panel size, which increases both the resistivity of the signal wire and the load capacitance, causes a great signal delay. Consequently, in a certain area inside the display area in the liquid crystal display, there might be a failure in which a desired voltage is not applied to the liquid crystal within a writing period, resulting in a state in which the liquid crystal is not sufficiently charged, that is, an insufficient charge-supply state. This state causes so-called shadowing, resulting in degradation in the display quality.
Referring to FIG. 19, the following description will discuss the shadowing. For example, as illustrated in FIG. 19, suppose that an image pattern (hereinafter, referred to as a shadowing pattern) is displayed so that only the area 31 in the center has a black display with the other areas having half-tone displays. Here, in FIG. 19, the area on the right side of the center area 31 is referred to as area 32, the area on the left side of the center area 31 is referred to as area 33, the areas above areas 31, 32 and 33 are referred to as area 34, and the areas below areas 31, 32 and 33 are referred to as area 35.
In the case of a normally white display, the black display has a greater liquid crystal capacitance than the white display. In other words, in the display state of this type, the load capacitance of a lateral signal wire contained in the areas 31, 32 and 33, that is, a lateral wire connected to the pixels that carry out a black display, is greater than the load capacitance of a signal wire contained in areas 34 and 35 due to the influence of area 31 having a black display. In other words, the signal delay in the lateral signal wire connected to the pixels that carry out a black display is greater in such a manner that depending on cases, there is a difference between the applied voltage to the liquid crystal at areas 32, 33 and the applied voltage to the liquid crystal at areas 34, 35. Consequently, in the areas located on both sides of the black display area, a desired voltage is not applied to the liquid crystal due to the signal delay, with the result that an insufficient charge occurs and these areas have a display different from that of the other halftone areas. This is a phenomenon referred to as the shadowing due to signal delay.
The above-mentioned description has discussed a problem with the enlargement of the panel size in the liquid crystal display, and a similar problem arises with an attempt to achieve the high precision. In other words, the high-precision apparatus makes the writing time of the signal shorter, and consequently becomes more susceptible to influences of a signal delay, thereby resulting in degradation in the display quality in the same manner as described above.
As described above, as an attempt is made so as to achieve the large-size panel and high precision in a liquid crystal display, problems arise from an increase in the resistivity of each signal wire, an increase in the load capacitance to each signal wire, a reduction in the writing time of the signal, etc., thereby causing a signal delay and the resulting degradation in the display quality such as the shadowing.
In order to reduce the signal delay as described above, and to eliminate an insufficient charge supply to the liquid crystal, effective methods are to reduce the resistivity of the signal wire and to minimize the load capacitance to the signal wire. More specifically, (1) in order to reduce the resistivity of the signal wire, a metal film forming the signal wire is made thicker, (2) in order to reduce the resistivity of the signal wire, the line width of the signal wire is made thicker, and (3) in order to minimize the load capacitance to the signal wire, the distance between the signal wires is widened. These arrangements make it possible to reduce the signal delay.
However, in the above-mentioned arrangement (1), since the metal film needs to be stacked thicker, the film-forming time of the metal film is prolonged, resulting in degradation in the productivity. Moreover, a difficult controlling process is required upon etching the metal film into a predetermined pattern, resulting in a reduction in the rate of non-defective products and high costs.
In the above-mentioned arrangements (2) and (3), the thickened signal wire or the widened distance between the signal wires causes a reduction in areas to be used as pixels, resulting in a reduction in the aperture ratio. The decreased aperture ratio decreases the transmittance and luminance of the liquid crystal display, resulting in degradation in the display quality.
As described above, the above-mentioned arrangements (1) to (3) tend to raise problems of a reduction in the rate of non-defective products and a decrease in the aperture ratio, resulting in high costs and degradation in the display quality.
Moreover, another arrangement may be proposed in which signals are inputted from both sides of the panel, that is, from both sides of each signal wire, so that it is possible to decrease the signal delay and also to compensate for the insufficient supply of charge. However, in order to input signals from both sides of the panel, it is necessary to install drivers for inputting signals on both sides of the panel. In other words, the number of drivers is doubled, resulting in a problem of very high costs.
Furthermore, with respect to the means for reducing the shadowing caused by the signal delay without modifying the design of the inside of the panel, a method for applying a voltage to each pixel by using a dot-inversion driving system. Here, an explanation will be given of the dot-inversion driving system and the line-inversion driving system.
First, referring to FIG. 23 and FIGS. 21(a) and 21(b), an explanation will be given of the line-inversion driving system. In the case when, as shown in FIG. 23, a signal is inputted to a certain scanning line 93 in such a manner that all the TFTs 92 connected to the scanning line 93 are turned on, supposing that a displayed image is a solid image, voltage signals having the same polarity are applied to all the adjacent gradation signal lines 94. In other words, all the voltages to be applied to the pixel electrodes 91 connected to the scanning line 93 have the same polarity.
When, upon completion of the scanning process for one line, such a signal as to turn all the TFTs 92 on is inputted to the next scanning line 93, applied voltage signals having a polarity reversed to that at the time of the previous scanning process preceded by one line are inputted to all the gradation signal lines 94. In other words, at this time, all the voltages to be applied to the pixel electrodes 91 connected to the scanning line 93 have the same polarity, with the polarity being reversed to that at the time of the previous scanning process preceded by one line.
FIG. 21(a) shows part of the state of the voltage polarity applied to each pixel at the time when the above-mentioned scanning process is repeated. When, after completion of the scanning process for one screen, a scanning process for the next screen is carried out, voltages having a polarity reversed to that at the time of the scanning process of the previous screen is applied to the pixel electrodes 91 for each line. FIG. 21(b) shows this state. More specifically, in the case when the line inversion driving is carried out, refreshing of the screen is carried out by repeating the state of FIG. 21(a) and the state of FIG. 21(b).
Next, referring to FIG. 23 and FIGS. 22(a) and 22(b), an explanation will be given of the dot-inversion driving system. In the case when, as shown in FIG. 23, a signal is inputted to a certain scanning line 93 in such a manner that all the TFTs 92 connected to the scanning line 93 are turned on, supposing that a displayed image is a solid image, applied voltage signals having respectively different polarities are inputted to the adjacent gradation signal lines 94. In other words, the voltages to be applied to the adjacent pixel electrodes 91 connected to the scanning line 93 have the respectively reversed polarities.
When, upon completion of the scanning process for the one line in question, such a signal as to turn all the TFTs 92 on is inputted to the next scanning line 93, applied voltage signals having a polarity reversed to that at the time of the previous scanning process preceded by one line are inputted to all the gradation signal lines 94. In other words, at this time, the voltages to be applied to the adjacent pixel electrodes 91 connected to the scanning line 93 have the respectively reversed polarities, with each polarity being reversed to that at the time of the previous scanning process preceded by one line.
FIG. 22(a) shows part of the state of the voltage polarity applied to each pixel at the time when the above-mentioned scanning process is repeated. When, after completion of the scanning process for one screen, a scanning process for the next screen is carried out, voltages having a polarity reversed to that at the time of the scanning process of the previous screen is applied to the pixel electrodes 91 for each line. FIG. 22(b) shows this state. More specifically, in the case when the line inversion driving is carried out, refreshing of the screen is carried out by repeating the state of FIG. 22(a) and the state of FIG. 22(b).
In the case of the line inversion driving system, when the shadowing pattern as shown in FIG. 19 is displayed, it is necessary for the common signal line 96 which is connected to the scanning electrode 93 to which the signal for turning the TFTs 92 on is inputted and the corresponding opposing electrodes to apply or remove a charge having the same polarity to or from all the pixel electrodes 91 connected to the scanning line 93. Therefore, this system is highly susceptible to an insufficient charge supply due to the signal delay, causing the generation of shadowing.
In contrast, in the case of the dot inversion driving system, voltages that are applied to the pixel electrodes 91 connected to one scanning line 93 have respectively reversed polarities with respect to the adjacent pixel electrodes 91; therefore, it is not necessary for the common signal line 96 to apply or remove a great charge. Therefore, this system is less susceptible to an insufficient charge supply due to the signal delay and the resulting shadowing.
Therefore, as described above, with respect to the method for reducing the shadowing caused by the signal delay, it is more effective to use a method for applying a voltage to each pixel by the dot inversion driving system.
However, the dot inversion driving system has the following limitations: a source driver capable of outputting a doubled voltage is required so as to allow the gradation voltages of the adjacent pixels to be amplified reversely to each other, and the common signal line 96 and the opposing electrode simultaneously form references for a plus charge and a minus charge so that it is possible to output a signal line voltage two times as much as that at the time of line inversion driving process. This causes other limitations such as the necessity of a source driver having a higher voltage resistant property. As a result, this driving system causes an increase in the cost of a source driver as compared with the line inversion driving system.
Here, as described above, in the above-mentioned opposing source construction, since the scanning lines and the gradation signal lines are formed on individually different substrates without intersecting each other on the same substrate; therefore, the rate of occurrence of line defects is reduced so that the yield is improved and the cost is decreased. Moreover, since no signal wires intersect each other on the same substrate, it is possible to reduce the capacitance imposed on the signal wires, and consequently to reduce the signal delay. However, as an attempt is further made to achieve large-size liquid crystal panels with higher precision, it becomes more difficult to produce them without causing degradation in the display quality and an increase in the costs.
Here, an explanation will be given of the fact that as compared with the current construction, the opposing source construction causes more problems in achieving large-size liquid crystal panels and higher precision. As shown in FIG. 23, in the current construction, the flow of image signals based upon image data is described as follows: The image signal is allowed to reach one of the pixel electrodes 91 from the gradation signal line 94 through the TFT 92 so that a voltage is applied to the liquid crystal between the pixel electrode 91 and the opposing electrode.
In contrast, in the opposing source construction as shown in FIG. 24, when an image signal is inputted to the gradation signal line 106, a current flows to the pixel electrode 104 from the reference signal line 103 through the TFT 101 so that a voltage is applied to the liquid crystal.
As described above, in the current construction, the output of the source driver connected to the respective gradation signal lines 94 and the reference voltage in the opposing electrode is used so as to apply a voltage to the liquid crystal. In contrast, in the opposing source construction, the output of the source driver connected to the respective gradation signal lines 106 and the reference voltage in the reference signal line 103 is used so as to apply a voltage to the liquid crystal.
In the current construction, it is the opposing electrode to which the reference voltage is inputted. This opposing electrode is generally formed by a transparent conductive film having a thickness of 1500 to 4500 xc3x85, and its width is set to approximately the same as the width of each pixel area. In other words, with respect to the opposing electrode, since its width is made comparatively wider so that the resistance is made comparatively smaller. In contrast, in the opposing source construction, it is the reference signal line 103 to which the reference voltage is inputted. Since this reference signal line 103 is formed by an opaque metal thin film, it is necessary to make its width as thin as possible so as not to cause a reduction in the aperture ratio in the liquid crystal panel. Therefore, the reference signal line 103 has a comparatively high resistivity. Consequently, as compared with the current construction, the opposing source construction tends to cause an insufficient supply of charge due to a signal delay in the reference signal line 103, resulting in large shadowing.
The objective of the present invention is to prevent shadowing in a liquid crystal display having an opposing source construction by eliminating an insufficient supply of charge to the liquid crystal due to a delay in the reference signal while maintaining the advantages of the opposing source construction, and consequently to provide a large-size liquid crystal display with high precision that is superior in display quality.
In order to achieve the above-mentioned objective, the liquid crystal display of the present invention, which comprises:
a pixel substrate;
an opposing substrate aligned face to face with the pixel substrate with a gap in between;
a liquid crystal layer that is sandwiched in the gap between the pixel substrate and the opposing substrate;
a plurality of pixel electrodes formed on the pixel substrate in a matrix format;
opposing electrodes formed on the opposing substrate in association with the pixel electrodes;
a plurality of scanning lines and a plurality of reference signal lines that are placed in parallel with each other in each of the border areas between the pixel electrodes on the pixel substrate;
a gradation signal line that is placed in a direction orthogonal to the scanning lines on the opposing substrate and that is electrically connected to the opposing electrodes; and
a switching element of a three-terminal type having respective terminals electrically connected to the scanning line, the reference signal line and the pixel electrode on the pixel substrate, is characterized by further comprising:
a reference signal main line that is placed so as to electrically connect the reference signal lines with each other on the periphery of the area in which the reference signal lines are placed; and
a voltage applying circuit for applying a reference signal voltage to a reference signal circuit constituted by the reference signal lines and the reference signal main line, and for controlling the applying voltage in response to voltage variations in the reference signal circuit,
wherein: the reference signal main line includes an input main line and an output main line, the input main line and the output main line being electrically connected to each other through the reference signal line, with their portions other than the connected portions through the reference signal line being in an electrically insulated state or in a high impedance state, and an input section for applying a voltage from the voltage applying circuit is placed in the input main line and an output section for feeding a voltage back to the voltage applying circuit is placed in the output main line.
In the above-mentioned arrangement, the input main line and the output main line are placed as the reference signal main line, the input main line and the output main line are electrically connected through the reference signal line, with their portions other than the connected portions through the reference signal line being in an electrically insulated state or in a high impedance state, and an input section for applying a voltage from the voltage applying circuit is placed in the input main line and an output section for feeding a voltage back to the voltage applying circuit is placed in the output main line; therefore, a voltage applied to the reference signal circuit through the input section is outputted from the output section after passing through the reference signal line. Consequently, the voltage applying circuit is allowed to accurately detect minute voltage variations caused by the respective reference signal lines inside the reference signal circuit, and can carry out a proper voltage-compensating process by adjusting the applying voltage based upon the detected voltage variations. With this arrangement, without a reduction in the aperture ratio caused by the widened line width of the reference signal line and the widened distance between the line gaps, it is possible to prevent shadowing caused by an insufficient supply of charge due to a delay in the reference signal, and consequently to provide a liquid crystal display that is superior in display quality.
Moreover, in the above-mentioned arrangement, the liquid crystal display has the so-called opposing source construction so that the scanning lines and the gradation signal lines are formed on independently different substrates; therefore, since the scanning lines and the gradation signal lines are not made to intersect each other on the same substrate, it is possible to reduce the rate of occurrence of line defects. Consequently, it becomes possible to improve the yield and also to reduce the production costs.
Here, xe2x80x9cthe state having a high impedancexe2x80x9d refers to a state having an impedance sufficiently greater than the impedance within a panel so as to allow accurate detection of voltage variations inside the panel.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.